Trench isolation for semiconductor devices

ABSTRACT

A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

BACKGROUND

The present invention relates generally to semiconductor devices and,more particularly, to trench isolation process technology for use inmemory, image, logic and other semiconductor devices.

Implementing electronic circuits involves connecting isolated devices orcircuit components through specific electronic paths. In siliconintegrated circuit (IC) fabrication, it is necessary to isolate devicesthat are formed in a single substrate from one another. The individualdevices or circuit components subsequently are interconnected to createa specific circuit configuration.

As the density of the devices continues to rise, parasitic inter-devicecurrents become more problematic. Isolation technology, therefore, hasbecome a critical aspect of integrated circuit fabrication.

For example, dynamic random access memory (DRAM) devices generallycomprise an array of memory cells for storing data and peripheralcircuits for controlling data in the memory cells. Each memory cell in aDRAM stores one bit of data and consists of one transistor and onecapacitor. Within the array, each memory cell must be electricallyisolated from adjacent memory cells. The degree to which large numbersof memory cells can be integrated into a single IC chip depends, amongother things, on the degree of isolation between the memory cells.

Similarly, in metal-oxide-semiconductor (MOS) technology, isolation mustbe provided between adjacent devices, such as NMOS or PMOS transistorsor CMOS circuits, to prevent parasitic channel formation. CMOS circuitscan be used, for example, to form the pixels in a photosensitive imagingdevice and must be isolated from one another. In the case of CCD or CMOSimagers which are intentionally fabricated to be sensitive to light, itis advantageous to provide both electrical and optical isolation betweenpixels.

Shallow trench isolation (STI) is one technique which can be used toisolate devices such as memory cells or pixels from one another. Ingeneral, a trench is etched into the substrate to provide a physicalbarrier between adjacent devices. Refilled trench structures, forexample, consist essentially of a sub-micron recess formed in thesilicon substrate by a dry anisotropic or other etching process. Therecess is filled with a dielectric such as a chemical vapor deposited(CVD) silicon dioxide (SiO₂). The filled trench then is planarized by anetchback process so that the dielectric remains only in the trench andits top surface level with that of the silicon substrate.

Refilled trench isolation is sometimes categorized according to thedimensions of the trench: shallow trenches (less than about 1 micron),moderate depth trenches (1-3 microns), and deep narrow trenches (greaterthan 3 microns deep, less than 2 microns wide). Shallow trench isolationis used, for example, to isolate devices.

To enhance the isolation further, ions can be implanted in the siliconsubstrate in the area directly beneath the trench. However, as noted,for example, in S. Nag et al., “Comparative Evaluation of Gap-FillDielectrics in Shallow Trench Isolation for Sub-0.25 μm Technologies,”IEEE IEDM, pp. 841-844 (1996), some ion implants can result in highcurrent leakage. In particular, when ions are implanted in the substrateclose to the edges of the trench, current leakage can occur at thejunction between the active device regions and the trench. Similarly, ifthe trench is shallow, then a photon impinging on a particular pixel ofa photosensitive device may diffuse under the trench isolation structureto an adjacent pixel, resulting in detection of the photon by the wrongpixel. Accordingly, it is desirable to improve the trench isolationtechniques to address those and similar problems.

SUMMARY

In general, according to one aspect, a method of fabricating anintegrated circuit includes forming an isolation trench having a bottomand sidewalls in a semiconductor substrate and partially filling thetrench with a dielectric material so that at least the sidewalls of thetrench are coated with the dielectric material. Ions are implanted intothe substrate in regions directly below the isolation trench afterpartially filling the trench with the dielectric material.

The dielectric along the sidewalls of the trenches can serve as a maskso that substantially all of the ions implanted below the isolationtrenches are displaced from the active regions. After the ions areimplanted in the substrate below the trenches, the remainder of thetrench can be filled with the same or another dielectric material.

Various implementations include one or more of the following features.In general, the energy of the ions and the thickness of the dielectriclayer can be selected so that the dielectric layer along the sidewallsof the trench serves as a mask that prevents ions from becomingimplanted in the substrate in a vicinity near edges of the trenches.Depending on the particular application, shallow and/or deep ionprofiles can be implanted into the substrate.

Partially filling the trench with a dielectric material can includegrowing an oxide layer such as silicon dioxide or depositing aninsulating material using chemical vapor deposition or a combination ofthermal growth and chemical vapor deposition. Preferably, the dielectriclayer has a sidewall thickness less than about forty percent the widthof the trench.

The trench isolation technique can be used to fabricate a variety ofintegrated circuits which can include devices that exhibit reducedcurrent leakage and/or reduced optical cross-talk. Integrated circuitsincluding imaging devices, such as CMOS imagers and CCD imagers, memorydevices, such as DRAMs, and logic devices are representative of devicesthat can be formed according to the invention. More generally, thetechniques described by this invention can be used to provide isolationfor an active region on any semiconductor device. Impurity-doped regionscan be formed in the active regions and may include, for example,storage nodes for a memory device, photosensitive elements for animaging device, or active elements for a logic device, as well as othersactive semiconductor elements.

In some implementations, shallow ion implants are provided to establishfield threshold voltage implants to improve the electrical isolationbetween active areas. Deep implants can be provided, for example, toreduce the optical cross-talk between adjacent photosensitive pixels inCMOS or CCD imagers.

Other features and advantages will be readily apparent from thefollowing detailed description, the accompanying drawings, and theclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of an exemplary semi-conductor device with aphotolithographic mask for the formation of trench isolation regions.

FIG. 2 is a cross-section of the device with isolation trenches formedtherein.

FIG. 3 is a cross-section of the device after the trenches have beenpartially-filled with a dielectric according to the invention.

FIG. 4 is a cross-section of the device during an ion implant accordingto the invention.

FIG. 5 is a cross-section of the device during an ion implant accordingto another embodiment of the invention.

FIG. 6 is a cross-section of the device after the trenches have beencompletely filled according to the invention.

FIGS. 7-8 illustrate subsequent acts in the fabrication process of thedevice.

FIG. 9 illustrates an exemplary DRAM incorporating the invention.

FIG. 10 illustrates an exemplary imager incorporating the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, a silicon or other semiconductor wafer 10 includesa bulk substrate region 12. Typically, ions are implanted in thesubstrate 12 to form n-type wells and p-type wells which define thelocations of the n-channel and p-channel devices 26. For example, thesubstrate 12 can be implanted with a p-type dopant such as boron (B) toform a p-well 13. For ease of illustration, the figures show activeareas and STI field isolation regions in a single well type. However, ingeneral, the invention is applicable to other semiconductor deviceisolation regions such as n-well and p-well regions in p-typesubstrates, n-type substrates and epitaxial substrates, including p onp+, p on p−, n on n+, and n on n−. In some implementations, thesubstrate 12 can comprise gallium arsenide (GaAs) or other semiconductormaterials such as InP, CdS, CdTe and the like.

A layer of pad oxide 14 is provided atop the substrate 12, for example,either by deposition or by oxidizing conditions. A sacrificial layer 16such as Si₃N₄ is provided over the pad oxide layer 14 and defines anouter surface 18. A mask 20, such as a layer of photoresist, then isdeposited and patterned as shown. The mask 20 can be patterned byconventional photolithographic techniques.

Referring to FIG. 2, the sacrificial layer 16 and the pad oxide layer 14are etched by a dry etch process. The etch process is allowed tocontinue into the substrate 12 to form one or more trenches 22. In oneimplementation, the trenches 22 extend into the substrate 12 to a depthof about 1,000 to about 8,000 Å. An anisotropic etch such as a plasma orreactive ion etch (RIE) process can be used as the dry etch. The mask 20then is removed by wet or dry stripping of the photoresist.

Next, referring to FIG. 3, the trenches 22 are partially filled with adielectric material 24. Suitable dielectric materials include oxidessuch as silicon oxide (SiO₂). The oxide can be formed by thermallygrowing a thin layer of SiO₂ over exposed areas of the substrate andsubsequently depositing another layer of SiO₂ by a chemical vapordeposition (CVD) technique. The thermally-grown oxide layer serves topacify the silicon surfaces of the bulk substrate 12 from thesubsequently deposited CVD oxide.

According to one embodiment, the dielectric layer 24 is substantiallyconformal. In other words, the thickness of the dielectric layer 24 issubstantially the same along the sides and at the bottom of the trenches22, as well as above the active regions 26 of the device. For example,using trenches 22 having a width of about 3,000 Å and a depth of about3,500 Å into the substrate 12, an oxide 24 having a thickness of about100 to about 1,200 Å can be provided. The width of the gap that existsbetween opposite walls 28 of the trench 22 after the oxide 24 has beengrown is, therefore, about 600 to about 2,800 Å. In general, thethickness of the oxide layer 24 along the sidewalls 28 should be atleast about 100 Å. In general, the thickness of the oxide 24 along thesidewalls 28 should not be greater than about forty percent the originalwidth of the trench 22.

Once the trenches 22 have been partially filled with the dielectric 24,a masked ion implant is performed to implant ions in the areas of thesubstrate 22 directly beneath the trenches 22 as shown in FIG. 4. Forexample, in the case of a p-type substrate 12 with p-wells, p-type ionssuch as boron (B) can be implanted in the substrate using a photoresistmask 30. Similarly, in the case of a p-type substrate 12 with n-wells,n-type ions such as phosphorous (P), arsenic (As) or antimony (Sb) canbe implanted.

Performing the isolation ion implant while the trenches 22 are onlypartially filled with an oxide or other dielectric 24 allows the oxidealong the trench walls 28 to serve as a mask that prevents the ions frombecoming implanted in the substrate near the edges of the trenches.Thus, an implanted ion profile can be obtained so that the implantedions are displaced from the sidewall edges of the trench 22 by adistance approximately equal to the sidewall thickness of the dielectriclayer 24. In particular, shallow and/or deep ion implants which areself-aligned to the edge of the active regions 26 can be obtained. Theactual profiles may differ from those illustrated in the drawings.

A shallow implant, in other words, an implant with ion energies justhigh enough to pass through the dielectric layer 24 at the bottom of thetrench 22, is advantageous because it is self-aligned to the trench edgeand it is spaced away from the trench edge. Such a shallow implant canbe effective as a field threshold voltage (V_(t)) implant to improve theelectrical isolation between active areas separated by the trenchisolation regions. In contrast to existing STI processes, which sufferfrom leakage from the active areas to the substrate, the presenttechnique, in which the field implant is spaced away from the STI trenchedge and the subsequently-formed active areas, creates a reduced dopingprofile at the trench edge. The reduced doping profile can result in areduced electric field and reduced leakage.

Alternatively, or in addition, a deep ion implant can be formed beneaththe trench 22 with the implant having a depth at least as great as thedepth of the dielectric layer 24. The range of such a deep implant canapproach the depth of the STI trench. Preferably, the depth of the ionimplant below the trench 22 should not be greater than the combinedthicknesses of the pad oxide layer 14 and the sacrificial layer 16 plusthe depth of the trench 22. More generally, the depth of the deep ionimplant into the substrate should be in the range of about 10 to 100percent the depth of the trench. Preferably, the ions are implanted to adepth in the range of about 20 to 80 percent the depth of the trench.The deep implant can be spaced away from the trench edge to reduce theleakage from the active areas to the substrate. A deep implant can forma deep isolation region without added substrate leakage which isadvantageous for applications such as CCD and CMOS imagers. In thoseapplications, absorption of long wavelength light occurs deep in thephotosensitive pixels thereby creating photo-generated carriers deep inthe silicon that can diffuse to neighboring pixels. The presence of thedeep field implant between pixels serves to collect the photo-generatedelectrons and thereby prevent them from being collected at a neighboringpixel site. The deep implant can, therefore, reduce optical cross-talkand help preserve the fidelity of the image obtained by the imager.

In an alternative embodiment illustrated in FIG. 5, an oxide or otherdielectric layer 24A with poor conformality partially fills the trenches22. In particular, a relatively thick SiO₂ layer can be grown above theactive regions 26 whereas a relatively thin SiO₂ layer is grown alongthe walls 28 and bottom of each trench. For example, the thick oxidelayer 24A above the active regions 26 can be about two to four times asthick as the oxide in the trenches. As before, the oxide layer 24A alongthe walls 28 of the trenches 22 can serve as a mask that prevents theions from becoming implanted in the substrate in the vicinity near theedges of the trenches, and an implanted ion profile can be obtained sothat most of the implanted ions are displaced from the active regions 26of the device 10. A shallow boron or other ion implant can then beperformed with self-alignment to the edges of the active regions 26.Performing a shallow isolation ion implant while the trenches 22 areonly partially-filled with a dielectric having poor conformality can beadvantageous, for example, in the fabrication of DRAMs.

Once the ions are implanted beneath the partially-filled trenches 22 asshown, for example, in FIG. 4, a CVD oxide 34 is deposited to fill thetrenches completely as shown in FIG. 6. After deposition of the CVDoxide 34, an anneal process can be performed to densify the oxide priorto CMP planarization. The anneal process also serves to activate thefield implants.

Subsequently, the top surface of the device is planarized by an etchbackprocess which can include, for example, a chemical-mechanical polish(CMP). The top surface is etched at least to the sacrificial layer 16 toform a field isolation region 36 as shown in FIG. 7. Remaining portionsof the sacrificial layer 16 are etched from the substrate. For example,if the sacrificial layer 16 comprises silicon nitride (Si₃N₄),phosphoric acid (H₃PO₄) can be used for the etch. The previously-formedoxide layer 14 is stripped and a new oxide layer 38 is grown as a gateoxide (FIG. 8). Alternatively, the oxide layer 14 can be stripped and anew sacrificial oxide layer grown. The ions would then be implantedthrough the new sacrificial layer which subsequently is stripped orremoved. The new gate oxide 38 then can be grown.

Additional processes can be performed using known techniques to completean integrated circuit (IC) that includes active semiconductor regionsseparated by the isolation regions 36. Various types of devices can beformed in the active areas. Such devices include imaging devices, memorydevices or logic devices. For example, the completed IC can include anarray of light sensitive pixels for a CMOS or CCD imager, or an array ofmemory cells for a DRAM or other memory device. In other ICs, logicdevices for gate arrays, microprocessors or digital signal processorscan be formed in the active regions. The field isolation regions 36 canseparate the active regions from one another.

FIGS. 9 and 10 illustrate portions of exemplary integrated circuitswhich include isolation regions separating active regions. The isolationregions can be formed using the techniques described above.

Referring to FIG. 9, a stacked-cell DRAM 40 includes a semiconductorsubstrate 42 with multiple active regions 44A, 44B, 44C separated byshallow trench field isolation regions 46A, 46B. Impurity-doped regions52, 53 can be formed, for example, by a diffusion implanted process withthe regions 52 serving as storage nodes for memory cells of the DRAM.Stacked gates are provided over the gate oxide layers 56 with nitride orother spacers 58 provided on either side of the gates. The stacked gatesinclude a polysilicon layer 54 and an insulating layer 55. Theinsulating layer 55 can include, for example, a deposited oxide, adeposited nitride, or a composite stack of oxide/nitride oroxide/nitride/oxide layers. In some implementations, each gate stackalso includes a silicide layer between the polysilicon layer 54 and theinsulating layer 55. The silicide layer can include, for example, atungsten silicide, a titanium silicide or a cobalt silicide. In yetother implementations, the gate stack includes a barrier metal layer anda metal layer between the polysilicon layer 54 and the insulating layer55. Suitable barrier metal layers include tungsten nitride, titaniumnitride and tantalum nitride. The metal layer can include tungsten,tungsten silicide, titanium silicide, or cobalt silicide. Polysiliconplugs 60 form the contacts to the drain and source regions 52.

Each isolation region 46A, 46B includes dielectric layers 48, 50 whichare formed when the isolation trenches are partially and completelyfilled, respectively. Ion implanted regions are provided in thesubstrate 42 directly below the dielectric layer 48 and are formedaccording to the techniques described above. The ions implanted beneaththe dielectric layer are displaced from the active regions by a distanceapproximately equal to the sidewall thickness of the dielectric layer48. In some embodiments, that distance is at least about 100 Å.

In the illustrated integrated circuit of FIG. 9, capacitor cellscomprise lower storage node electrodes 62, a cell dielectric 64 and anupper electrode 66. A metal contact 68 provides the electricalconnection between one of the plugs 60 which serves as the bit line anda first metallization layer 70. An insulating layer 72 separates thefirst metallization layer 70 from a second metallization layer 74. Theentire semiconductor wafer is covered by a passivation layer 76.

Although FIG. 9 illustrates a stacked-cell DRAM, isolation regionsformed according to the techniques described above can be incorporatedinto any other type of memory such as trench cell DRAMs, flash memory,embedded memory, electrically erasable programmable read only memory(EEPROM), and the like.

Referring now to FIG. 10, a photodiode type of CMOS imager 80 includes asemiconductor substrate 82 with multiple active regions 84A, 84B, 84Cseparated by field isolation regions 86A, 86B. The active regions 84A,84B, 84C form photosensitive pixels each of which includesimpurity-doped regions 92, 92A, 92B. The region 92A serves as a floatingdiffusion region, and the region 92B serves as a photodiode. Thefloating diffusion region 92A is electrically connected to the gate of asource follower transistor 100 as shown in FIG. 10.

Polysilicon gates 94, including a transfer gate and a reset gate, areprovided over respective gate oxide layers 96 with nitride or otherspacers 98 provided on either side of the gates. In someimplementations, additional layers are formed over the polysilicon layer94 to form a gate stack. Thus, a silicide layer or a silicide layercovered by an insulating layer can be provided over the polysilicon gate94. The silicide layer can include, for example, a tungsten silicide, atitanium silicide or a cobalt silicide, and the insulating layer caninclude, for example, a deposited oxide, a deposited nitride, or acomposite stack of oxide/nitride or oxide/nitride/oxide layers. In yetother implementations, a gate stack is formed by a barrier metal layerand a metal layer provided over the polysilicon layer 94. Optionally, aninsulating layer can be provided over the metal layer. Suitable barriermetal layers include tungsten nitride, titanium nitride and tantalumnitride. The metal layer can include tungsten, tungsten silicide,titanium silicide, or cobalt silicide.

Each isolation region 86A, 86B includes dielectric layers 88, 90 whichare formed when the isolation trenches are partially and completelyfilled, respectively. Shallow and deep ion implant regions are providedin the substrate 82 directly below the dielectric layer 88 and areformed according to the techniques described above. The ions implantedbeneath the dielectric layer are displaced from the active regions by adistance approximately the sidewall thickness of the dielectric layer88. In some embodiments, that distance is at least about 100 Å.

Although FIG. 10 illustrates a photodiode type of imager, isolationregions formed according to the techniques described above can beincorporated into photogate, photoconductor imagers and CCD imagers aswell.

Other implementations are within the scope of the following claims.

1-67. (canceled)
 68. An imaging device comprising: a semiconductorsubstrate including a plurality of doped active pixel regions, saidsemiconductor substrate having a first doping concentration; a fieldisolation region separating at least two of said active pixel regions,wherein said active pixel regions contain a photosensitive element,wherein said field isolation region includes an isolation trench, saidisolation trench further including a first area filled with a firstdielectric material forming at least sidewalls of said isolation trench,said sidewalls having a thickness, and a second area filled with asecond dielectric material situated within said sidewalls, said firstdielectric material being different than said second dielectricmaterial; and an ion implanted region provided below said second areahaving an increased doping concentration due to additional dopants in anarea of said substrate between said separated active pixel regions, saidincreased doping concentration being higher than said first dopingconcentration of said substrate, wherein substantially all ions fromsaid ion implanted region which increase said doping concentration aredisplaced away from said active pixel regions by a distance at leastequal to a said sidewall thickness of said first area filled with saidfirst dielectric material, and wherein said sidewall thickness of saidfirst area is less than about forty percent the width of the isolationregion and said sidewalls are arranged and configured to mask thesubstrate from said additional dopants.
 69. The imaging device of claim68, wherein the first dielectric material has a thickness of at leastabout one hundred angstroms.
 70. The imaging device of claim 68, whereinthe implanted ions establish a field threshold voltage.
 71. The imagingdevice of claim 68, wherein the ions are implanted into the substrate toa depth in a range of about 10 to 100 percent the depth of said firstarea filled with said first dielectric material.
 72. The imaging deviceof claim 68, wherein the ions are implanted into the substrate to adepth in a range of about 20 to 80 percent the depth of said first areafilled with said first dielectric material.
 73. The imaging device ofclaim 68, wherein said first area also includes said first dielectricmaterial provided on a bottom of said isolation trench and said seconddielectric material provided over said first dielectric materialprovided at said bottom.
 74. The imaging device of claim 68, whereinsaid thickness of said sidewalls is sufficient to block said additionaldopants from becoming implanted in the substrate near said active pixelregions, the doped region having an implanted ion profile in whichimplanted ions are displaced from an alignment with said active pixelregions by masking due to said sidewall thickness.
 75. The imagingdevice of claim 68, wherein the ion implanted region includes respectiveshallow and deep implants.
 76. The imaging device of claim 75, whereinthe shallow implants establish a field threshold voltage, and whereinthe deep implants are implanted into the substrate to a depth in a rangeof about 10 to 100 percent the depth of said first area filled with saidfirst dielectric material.
 77. The imaging device of claim 75, whereinthe implanted ions have a conductivity type that is the same as thesubstrate.
 78. The imaging device of claim 68, wherein the imagingdevice is a CMOS imager or a CCD imager.
 79. An imaging devicecomprising: a semiconductor substrate including a first region of apredefined conductivity type; a field isolation region for separatingsaid first region into at least two active pixel regions, each of saidpixel regions containing a photosensitive element, wherein said fieldisolation region includes an isolation trench, said isolation trenchfurther including a first dielectric material forming sidewalls of saidisolation trench and provided on a bottom of said isolation trench, anda second dielectric material situated within said sidewalls and providedover said first dielectric material, said first dielectric materialbeing different than said second dielectric material; and a doped regionformed within said first region and below said isolation trench, saiddoped region being of said predefined conductivity type and having adoping concentration higher than a doping concentration of said firstregion, wherein additional dopants in said doped region causing saidhigher dopant concentration are displaced away from said separatedactive pixel regions by said sidewalls being arranged and configured tomask said substrate from said additional dopants.
 80. The imaging deviceof claim 79, wherein the first dielectric material has a thickness of atleast about one hundred angstroms.
 81. The imaging device of claim 79,wherein the doped region extends into the substrate to a depth in arange of about 10 to 100 percent the depth of said isolation trench. 82.The imaging device of claim 79, wherein the doped region extends intothe substrate to a depth in a range of about 20 to 80 percent the depthof said isolation trench.
 83. The imaging device of claim 79, whereinsaid thickness of said sidewalls is sufficient to block said additionaldopants from becoming implanted in the substrate near said active pixelregions, the doped region having an implanted ion profile in whichimplanted ions are displaced from an alignment with said active pixelregions by masking due to said sidewall thickness.
 84. The imagingdevice of claim 79, wherein the doped region includes respective shallowimplanted dopants and deep implanted dopants.
 85. The imaging device ofclaim 84, wherein the shallow implanted dopants establish a fieldthreshold voltage, and wherein the deep implanted dopants are implantedinto the substrate to a depth in a range of about 10 to 100 percent thedepth of said isolation trench.
 86. The imaging device of claim 84,wherein the shallow implanted dopants and deep implanted dopants have aconductivity type that is the same as the substrate.
 87. An integratedcircuit comprising: a semiconductor substrate including a first regionof a predefined conductivity type; a field isolation region forseparating said first region into at least two active pixel regions,each containing a photosensitive element, wherein said field isolationregion includes an isolation trench, said isolation trench furtherincluding a first dielectric material forming sidewalls of saidisolation trench and provided on a bottom of said isolation trench, anda second dielectric material situated within said sidewalls and providedover said first dielectric material, said first dielectric materialbeing different than said second dielectric material; and a doped regionformed within said first region and below said isolation trench, saiddoped region being of said predefined conductivity type and having adoping concentration higher than a doping concentration of said firstregion, wherein additional dopants in said doped region causing saidhigher dopant concentration are displaced away from said separatedactive pixel regions by said sidewalls being arranged and configured tomask said substrate from said additional dopants.